Common Emitter (CE) Amplifier | Operating Point

The Operating Point of Common Emitter Amplifier

From the study of transistor characteristics, we find that amplification by transistor amplifier is most linear when the transistor operates in its active region. Hence the operating point must be suitably placed in the middle of the active region by suitable selection of external energy associated biasing circuit.

Circuit Description of Common Emitter (CE) Amplifier

Figure 1 gives the basic circuit of CE amplifier using NPN transistor bias through use of resistor R_b. Here capacitor C_b1, acts as the coupling capacitor to couple the input signal to the base-to-emitter terminals of the transistor. One end of the input voltage V_i is at the ground potential. Vcc is the collector supply voltage which serves the additional function of providing the bias current I_B. Under zero signal condition, C_b1 acts as an open circuit since the reactance of a capacitor is infinity at zero frequency (dc).

Thus, the capacitor C_bl acts as blocking capacitor. Normally C_b1 is chosen so large that at the lowest signal frequency, its reactance is small enough to be considered as a short circuit. Thus, capacitor C_b1 blocks dc voltage but passes a.c. signal voltage. Similarly, capacitor C_b2 serves the same two functions. Thus, C_b2 works as coupling capacitor and feeds the amplified a.c. signal to constitute the output voltage V₀ across RL. Simultaneously C_b2 blocks the d.c. voltage. Thus, the amplified output a.c. voltage may be applied to the input of the next amplifier stage without affecting the bias of the next stage.

DC and AC Load Lines | Common Emitter (CE) Amplifier

For given collector characteristics and transistor biasing, selection of proper operating point involves selection of suitable values of R_c and Vcc.

Collector current Ic is a function of V_CE and base bias current I_B and may be put mathematically as,

$I_C = f (V_{CE},I_{B})$ …..(1)

Equation 1 represents the static output characteristic of the CE transistor for base current I_B.

On applying Kirchhoff’s voltage law (KVL) to the collector circuit including only R_C. (excluding C_b2 and R_L) We get,

$V_{cc} = I_C R_c + V_{CE}$ …..(2)

Equation 2 represents a straight line having intercept Vcc on the voltage axis and intercept $\dfrac{V_{CC}}{R_c}$ on the current axis. The slope of this line equals $\dfrac{-1}{R_c}$ . This line is referred to as the load line and represents the dynamic characteristic of the device. The zero-signal operating point must be suitably located on this load line. This, in turn, depends on the value If R_L. If $R_L = \infty$ , R_L can be neglected and then for large symmetrical input signal (base current in this case), the operating point P₁ should be located in the centre of the dc load line. Vc and Ic are the zero-signal collector voltage and collector current respectively at the operating point. Next on application of a time varying signal, base current varies symmetrically on either side of I_B1, the point of operating moves along dc load line symmetrically about the zero-signal operating point P₁ and the instantaneous collector voltage and collector current vary approximately symmetrically about the zero-signal values Vc and Ic respectively.

If $R_L \neq \infty$ , then through the zero-signal operating point P₁, we draw an a.c. load line for load resistance R_L’ = R_L || R_c as shown in figure 3. On application of a time varying input signal (base current), the operating point moves symmetrically about P₁ along the a.c. load line. It is evident from Fig. 2 that the maximum swing of the input signal about zero signal point P₁is approximately 40 uA. For larger input signal swing say 60 uA, during negative excursion exceeding 40 uA, the collector current becomes zero.

Thus, this zero-signal operating point P₁ serves satisfactorily if the input signal swing does not exceed 40 uA. For larger input signal swing, say 60 uA, a more suitable quiescent operating point has to be selected. In order to avoid cutoff during the low current region of the cycle, the quiescent operating point should be located at a higher current on the dc load line. This selection is by trial and error. Thus, suppose we select P₂ as the quiescent operating point as shown in Fig. 2. This permits maximum input signal swing of 60 uA without cutoff in the low current region and without nonlinearity in the high current region.

Fixed Bias Circuit:

Amplifier of Fig. 1 uses fixed bias. In this circuit, the zero-signal operating point P₂ may be established by selecting resistance R_b such that the base current I_B equals the current I_B2 corresponding to the zero-signal operating point P₂.

Thus, $I_B = \dfrac{V_{CC}-V_{BE}}{R_b} = I_{B2}$ …..(3)

But V_BE across the forward biased emitter junction J_E is very small, being only about 0.2-volt (0.6 volt) in Ge (Si) transistor. Thus V_CC >> V_BE. Hence neglecting V_BE, Equation 3 yields,

$I_B \approx \dfrac{V_{CC}}{R_b}$ …….(4)

Thus, bias current I_B is constant and the circuit constitutes a fixed bias circuit.

Waveforms of output voltage and Current

Let $R_L = \infty$ and let P₁ be the zero-signal operating point on d.c. load line for base bias current I_B = 40 uA as shown in Fig. 3. Let a sinusoidal signal a.c. base current of amplitude 40 uA be applied at the input. This signal gets superimposed on the bias base current I_B1 ( = 40 uA). As the base current varies with time, collector current and collector voltage also change with time as shown in Fig. 3. This a.c. collector current forms an amplified version of the input base current.

It is evident that with properly selected zero signal operating point, the output signal is not distorted. In case, the operating point P₁ is placed at I_B 20 uA, then with input signal current of amplitude 40 uA there results negative peak clipping of collector current i_C and similar clipping of collector voltage v_C resulting in distortion. similarly, if point P₁ is placed at say I_B = 80 uA, then again with input signal current of amplitude 40 uA, there results positive peak clipping of collector current and corresponding distortion of collector voltage V_C.

ln Fig 3, we have used the d.c. load line. If $R_L \neq \infty$ , we should use the a.c. load line. In that case, the zero-signal operating point P₁ should be selected in the middle of the a.c. load line.

Causes of Shift of Zero Signal (Quiescent) Operating Point

We have seen that proper selection of quiescent operating point in vital for linear amplification. But the quiescent operating point may shift due to the following reasons.

Change of $\beta$ on transistor replacement
Thermal variations

Let us consider these aspects.

Transistor Replacement Discrete transistors of the same nomenclature and manufactured by the same firm have widely different values of device parameters including $\beta$ . Hence when a transistor in a given circuit is replaced by another of the same type, the transistor characteristics change somewhat and the quiescent operating point shifts.
Thermal Variations. A rise in temperature Causes three effects:

increase in I_CBO (or I_CO). Thus, I_CBO doubles for every 10°C rise in temperature
V_BE reduces at the rate of 2.5 mV/deg C rise in temperature
$\beta$ increases with the rise in temperature.

Here apart from ambient temperature variations, internal causes also have to be considered. Thus, any increases in I_C causes rise in temperature of collector junction J_C which in turn causes rise in I_CO. this rise in I_CO causes further rise in I_C. this in cumulative process and may damage the device unless adequate means are adopted to remove heat from the device. Even when damage of the device does not take place, there results considerable shift of the quiescent operating point i.e. thermal run away is said to take place.

Thus, operating point P may shift from the middle of the active region to saturation. We know that: $I_C = \beta I_B + (\beta + 1) I_{CBO}$ . Then even if we assume $\beta$ to be temperature invariant, for I_B = 0, with increase of temperature, output characteristics of CE transistor move up because of the rise in I_CBO. For nonzero value of I_B, the I_C versus V_CE curves also move up by the same amount. Hence the operating point moves up.

Increase of $\beta$ with rise of temperature causes further upward movement of quiescent operating point.

Means of Achieving Operating Point Stability

Operating point stability may be achieved in the following ways:

By using stabilization methods: use of proper biasing circuit, which permits such a variation of the base biasing current I_B as to maintain I_C almost constant in spite of variation of I_CO, V_BE and $\beta$ ..
By using Compensation methods: use of compensation elements such as diode, transistor, thermistor etc. theses device produce compensating voltage and currents and thus maintain the operating point stable.

Additional means are adopted to maintain the ambient and the junction temperatures constant. Thus, air conditioning or thermostat chamber (wherever possible) may be used to maintain the ambient or case temperature constant. Heat sink and air blast may be used to remove heat from the transistor.

We here take up only a brief study of biasing method for operating point stabilization.

Desired features of Biasing Methods: The biasing circuit used in transistor should be such as:

To establish conveniently the operating in the middle of the active region of the characteristics.
To make the operating point independent of transistor parameters.
To stabilize the collector current against temperature variations.

Different Biasing Methods: Various biasing method possible are:

Two battery bias
Fixed bias
Collector-to-base bias
Fixed bias with emitter circuit resistor
Self-bias

Out of theses method, the self-bias is the one most effective and convenient ands is, therefore, almost always used. We, therefore, take up here the study of this biasing method only.

Self-Bias (Emitter Bias)

Figure 4 gives the circuit of CE amplifier using self-bias or emitter bias. This biasing method is most popular used because it produces excellent operating point stability. The d.c. component of current through the resistor R_e caused d.c. voltage drop V_E in the polarity shown in figure 4. this voltage drop causes a reverse bias at the emitter junction J_E. but R₁ – R₂ combination across the V_CC supply produces a positive d.c. voltage V_b at the base relative to the emitter. The net forward bias at the emitter junction J_E then equals (V_b – V_e)

Stabilization Action of Self Bias Circuit Any rise in temperature T causes rise in I_CBO and hence rise in I_C. This increased current through R_e causes increased dc voltage drop across R_e and results in reduced net emitter-to-base forward bias, reduced base current I_b and reduced collector current I_C. This reduction in I_C tends to cancel the rise in I_C as caused by temperature rise. Operating point stability is thus improved.